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[Other] allidt_20020616.tar

Description: idt的双口ram的读写接口程序，verilog 代码，并且有测试文档-Employing a dual-port ram reader interface program, Verilog code, and a test document
Platform: | Size: 44740 | Author: buttern | Hits:

[Other resource] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16232 | Author: 田世坤 | Hits:

[Other resource] ReadHexFile

Description: 将16进制文件转换成RAM可读的文件,verilog语言编写-229 to 16 documents into RAM readable document, verilog language
Platform: | Size: 521 | Author: 彭琦 | Hits:

[Other resource] altera_ram

Description: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。
Platform: | Size: 180374 | Author: panyouyu | Hits:

[Other resource] Synchronous_read_write_RAM

Description: Synchronous read write RAM verilog。经过modelsim se仿真。
Platform: | Size: 1104 | Author: lianlianmao | Hits:

[Other resource] dul_ram(yk)

Description: 关于双口RAM的Verilog HDL源码
Platform: | Size: 3091 | Author: 123 | Hits:

[Other] RAM

Description: 通过使用fpga，verilog语言来实现RAM的读写功能。-for ram reading and writing
Platform: | Size: 4600832 | Author: 言艳 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog 常用模块，包含设计模块和测试模块，如有ram, lifo等-verilog useful blocks
Platform: | Size: 1010688 | Author: 陆美希 | Hits:

[VHDL-FPGA-Verilog] RAM

Description: Nios ii双口ram,用于MCU通过nios ii进行双口ram通信,verilog格式.-Nios II dual port RAM, for MCU dual port RAM communication, through the Nios II Verilog format.
Platform: | Size: 2048 | Author: 刘泽 | Hits:

[VHDL-FPGA-Verilog] DULE-RAM

Description: 基于VERILOG的双口ram例子，比较简单，不是很复杂，入门了解就可以了。-Based on dual port ram VERILOG example, the relatively simple, not very complicated, entry understand it.
Platform: | Size: 101376 | Author: 张是非 | Hits:

[Other] Verilog-135-classic-design

Description: verilog的135个经典设计，适合初学者自学。内有FIR、数字钟、交通灯、串转并、ram、rom等等常用模块的完整verilog代码，以及测试程序。还有基本的设计源码-verilog of 135 classic design, suitable for beginners learning. There are FIR, complete verilog code for a digital clock, traffic lights, and turn string, ram, rom, etc. commonly used modules, and test procedures. There are basic design source
Platform: | Size: 116736 | Author: 王凌 | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 用verilog实现了IP核的使用，例化了一个RAM，用来进行读写操作，另外还编写了斐波那契数列来进行测试。-Using verilog to achieve the use of IP core, the instantiation of a RAM, used to read and write operations, in addition to the preparation of the Fibonacci sequence for testing.
Platform: | Size: 3072 | Author: east | Hits:

[VHDL-FPGA-Verilog] fpga

Description: pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)
Platform: | Size: 13411328 | Author: 峰语 | Hits:

[VHDL-FPGA-Verilog] pudn

Description: Encoders, decoders and RAM Model
Platform: | Size: 11264 | Author: sheldon01 | Hits:

[VHDL-FPGA-Verilog] 各种基础module打包下载全集

Description: 例如分频器，alu，ram的verilog实现(The implementation of divider, alu, ram etc. in verilog)
Platform: | Size: 7168 | Author: Harrypotterrrr | Hits:

[VHDL-FPGA-Verilog] ram rom verilog

Description: ram rom verilog hdl verilog
Platform: | Size: 5618 | Author: mamine2ia | Hits:

[VHDL-FPGA-Verilog] ARM_SOC

Description: ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM kernel leads to the JTAG interface, can connect the debugger to debug with keil-MDK!)
Platform: | Size: 688128 | Author: ldz13180882132 | Hits:

[VHDL-FPGA-Verilog] 实验九 计算机核心（CPU+RAM）的设计与实现

Description: 计算机组成原理的CPU实验，基于quartus平台(CPU experiment of computer organization principle, based on quartus platform)
Platform: | Size: 3360768 | Author: 丁丫头 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

[VHDL-FPGA-Verilog] Memory Verilog

Description: ROM,RAM (dual port)- Verilog
Platform: | Size: 1585 | Author: gsrwork2017@gmail.com | Hits:
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